1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to a control strategy to improve uniformity of circuit elements across the substrate area by controlling a lithography process.
2. Description of the Related Art
The fabrication of integrated circuits is accomplished by forming a large number of elements, such as transistors, capacitors, resistors and the like, on a single substrate, wherein semiconductive, conductive and insulating material layers are deposited, patterned and modified so as to finally obtain the circuit elements and any electrical connections in accordance with a basic circuit design. For instance, in a modern CPU (central processing unit), millions of field effect transistors, which represent the backbone of the circuit design, are commonly manufactured in accordance with specified design rules that substantially determine the performance of the completed circuit.
Generally, the physical size of the circuit elements, for instance of the field effect transistors, essentially determines the electrical behavior, for instance the operating speed, of the integrated circuit. Hence, a minimal variation during the manufacturing processes directly concerning the formation of circuit elements of critical size may result in a minimal variation of the sizes of circuit elements or portions thereof, which then, in turn, may result in a reduced overall operating speed as the total operating speed of a circuit or a functional block thereof is determined by the slowest component. It is therefore, important to control the manufacturing processes to be as uniform as possible within a single die area and also within the entire substrate surface bearing a large number of dies. In the fabrication of integrated circuits, a large number of individual process steps are typically involved, wherein most of the process steps are performed on a full wafer basis, i.e., the processes are performed simultaneously all over the substrate surface. However, the ever increasing size of the substrates used in the production of semiconductors may render it difficult to precisely control the process conditions to be uniform across the entire substrate. Thus, a local variation of the effects of a certain process may be generated, which, in turn, entails a variation of the electrical behavior. On the other hand, a few manufacturing processes may be performed only at a portion of the substrate, thereby allowing an improved controllability of the process conditions at specified substrate positions with respect to the process uniformity. For instance, a manufacturing sequence for complex integrated circuits may, among many others, include the following essential process steps, such as photolithography, etching, dopant implantation, annealing and metrology processes, wherein photolithography and metrology steps are usually process steps that are performed on substrate portions rather than all over the entire substrate surface in one step. Consequently, these processes performed only at portions of the substrate provide the possibility to detect local non-uniformities of the entire process flow by measurement and also offer the potential for compensating for detected process non-uniformities by adjusting process parameters of the lithography process in conformity with the measurement results.
In presently established process technologies, photolithography plays a dominant role, since the lithographic generation of a resist feature substantially determines the finally obtained critical dimension of an actual circuit element. A critical dimension (CD) of a circuit element may represent, for instance, a minimum feature size, such as a width of lines or spaces of a critical circuit pattern. For instance, a gate electrode of a field effect transistor is substantially a line-like circuit element, wherein the width thereof substantially determines the operating speed of the field effect transistor. Hence, great efforts are being made to precisely control the critical dimensions of resist features produced by photolithography, which are then used as an etch mask for a subsequent etch process to pattern a material layer. In photolithography, the process of transferring an image from a reticle into a UV sensitive photoresist layer was dominated for a long time by so-called wafer steppers, which generate a reduced image of the reticle on a specified portion of the substrate. The exposed substrate portion will also be referred to as the reticle field and typically includes a plurality of individual die, wherein the number of individual die depends on the size of the die, i.e., on the complexity of the integrated circuit to be formed in the die, and on the size of the reticle field that the wafer stepper is able to produce during a single exposure step. Recently, wafer steppers are increasingly replaced by so-called step and scan systems, briefly denoted as scanners, which use a synchronized scanning of the substrate and the reticle through a fixed slit arranged within the associated optics. Consequently, the scanning of the substrate and the reticle is typically controlled so as to minimize any exposure non-uniformities within the exposure field to thereby minimize a variation of critical dimensions of the circuit elements, as already a variation of the critical dimension of the order of one nanometer or even less may translate into a corresponding speed variation for the completed device. During the lithography process, many factors may contribute to a deviation from the target critical dimension, resulting in an increased variation across the reticle field. Some of these factors are the variations in resist thickness and variations of the development process, imperfections of the lens and the reticle and synchronization errors between the substrate and the reticle during the scanning operation. In order to minimize these errors in imaging a circuit pattern onto a substrate, the exposure process is controlled to adapt an exposure dose, i.e., an integrated intensity of UV radiation irradiated onto a defined position of the substrate, in accordance with measurement results of critical dimensions obtained by previously processed substrates.
In this respect U.S. Pat. No. 6,493,063 by Seltmann et al. discloses a method and an apparatus for reducing the variance of critical dimensions in a semiconductor device in that lens and reticle errors are measured and are then compensated for. In particular, the critical dimension of a die is measured and is used to create a critical dimension function CD (x,y), wherein “y” represents the direction of scan and “x” is perpendicular to the direction of scan for a lithography scanner. CD (x,y) is then used to determine the energy distribution, i.e., the exposure dose, as a two-dimensional function E(x,y). Finally, the two-dimensional function E(x,y) is separated into two orthogonal functions E(x) and E(y), wherein a variation in E(x) and E(y), i.e., a deviation from specified target values for these functions, is compensated for by correspondingly adapting the exposure dose or using gray filters or other means. In this way, the lithography-associated variations of critical dimensions may effectively be compensated for or at least significantly reduced.
As previously explained, a large number of process steps is involved in the production of integrated circuits, wherein each process step may contribute to a variation of critical dimensions and/or a variation of the electrical behavior of a circuit element owing to local process fluctuations, wherein the impact on the finally obtained circuit element depends on the specific process. For instance, the gate length is an important critical dimension, which is according to present technologies, determined, to a dominant part, by the photolithography process. However, the effective length of the channel, although substantially defined by the gate length, depends, among other things, on the profile of the dopant concentration forming PN-junctions in a channel region of the field effect transistor. The dopant profile, however, depends on implantation parameters and especially on parameters of a subsequent anneal process for activating dopants and curing, at least partially, implantation-induced damage of the crystalline semiconductor region. As a consequence, variations and local non-uniformities of the implantation process and/or the anneal cycles may also contribute to a variation of the device performance, which may not be compensated for by the above-described technique, since only CD-induced variations are taken into consideration.
In view of the problem identified above, there exists a need for enhanced control strategy that enables effective compensation for device performance variation caused by local process non-uniformities of a plurality of processes involved in manufacturing integrated circuits. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.